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Software-defined GPS receiver Implemented on the Parallella-16 Board

  • Daniel Olesen
  • , Jakob Jakobsen
  • , Per Knudsen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › peer-review

3 Citations (Scopus)

Abstract

This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver. The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor. The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).

Original languageEnglish
Title of host publicationProceedings of the 28th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2015)
PublisherInstitute of Navigation
Pages3171-3177
Number of pages7
ISBN (Electronic)978-151081725-8
Publication statusPublished - 2015
Externally publishedYes
Event28th International Technical Meeting of the Satellite Division of the Institute of Navigation, ION GNSS 2015 - Tampa, United States
Duration: 14 Sept 2015 → 18 Sept 2015

Conference

Conference28th International Technical Meeting of the Satellite Division of the Institute of Navigation, ION GNSS 2015
Country/TerritoryUnited States
CityTampa
Period14/09/15 → 18/09/15

Programme Area

  • Programme Area 1: Data

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