Software-defined GPS receiver Implemented on the Parallella-16 Board

Daniel Olesen, Jakob Jakobsen, Per Knudsen

Publikation: Bidrag til bog/rapport/konferenceproceedingsKonferenceartikel i proceedingspeer review

3 Citationer (Scopus)

Resumé

This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver. The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor. The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).

OriginalsprogEngelsk
TitelProceedings of the 28th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2015)
ForlagInstitute of Navigation
Sider3171-3177
Antal sider7
ISBN (Elektronisk)978-151081725-8
StatusUdgivet - 2015
Udgivet eksterntJa
Begivenhed28th International Technical Meeting of the Satellite Division of the Institute of Navigation, ION GNSS 2015 - Tampa, USA
Varighed: 14 sep. 201518 sep. 2015

Konference

Konference28th International Technical Meeting of the Satellite Division of the Institute of Navigation, ION GNSS 2015
Land/OmrådeUSA
ByTampa
Periode14/09/1518/09/15

Programområde

  • Programområde 1: Data

Fingeraftryk

Dyk ned i forskningsemnerne om 'Software-defined GPS receiver Implemented on the Parallella-16 Board'. Sammen danner de et unikt fingeraftryk.

Citationsformater